High data reliability, high speed of memory access, and low power consumption are features that are demanded from semiconductor memory. In recent years, there has been an effort to further increase the speed of memory access. Many synchronous integrated circuits in a semiconductor device perform operations based on a clock signal to meet critical timing requirements.
In order to assess performance of a pulse-signal transmission system, a window or “data eye” pattern may be evaluated. The data eye for each of the data signals defines the actual duration that each signal is valid after various factors affecting the signal are considered, such as timing skew, voltage and current drive capability, for example. In the case of timing skew of signals, it often arises from a variety of timing errors such as loading on the lines of the bus and the physical lengths of such lines. For example, a rank margining test (RMT) may be used to evaluate the window in order to assess performance tolerance of an input buffer in a semiconductor device. In the RMT, a reference voltage (VREF) level may be varied from a mid-point between a voltage of input high (VIH) and a voltage of input low (VIL) to test a margin of RMT as performance tolerance. The input buffer is required to operate without any errors even if the reference voltage shifts, as long as the reference voltage is in a predetermined range.
FIG. 1 is a block diagram of an apparatus 100 including a command delay adjustment circuit 130. The apparatus 100 may include a clock input buffer 110, a command input buffer 111, a command decoder circuit 120, the command delay adjustment circuit 130, signal trees 190 and 191 for a command signal and a clock signal, and an output buffer 195.
The command delay adjustment circuit 130 may include a DLL clock path and a command path. The DLL clock path may include a command replica 121, and a delay line 141 for the clock signal. The command replica 121 replicates a delay of the command decoder circuit 120 in providing an RdClk signal responsive to command signals CMD and a system clock signal SCLK_CMD signals. The command replica 121 may delay a SCLK_DLL signal and provide a delayed system clock signal SCLKD to the delay line 141. The command path includes a delay line 140 for the command signal and a dQ-Enable-Delay (QED) circuit 160. The command delay adjustment circuit 130 further includes a replica of the DLL clock path 151, a phase detector 170 and a DLL control circuit 180 which form a DLL circuit together with the delay line 141 for the clock signal.
The command delay adjustment circuit 130 may synchronize an output signal of the dQ-Enable-Delay circuit 160 with a DLL clock signal DllClk from the delay line 141 while providing a latency on the output signal of the dQ-Enable-Delay circuit 160. The latency here is, for example, a column address strobe (CAS) latency (CL), which may be set based on a clock frequency of the clock signal CK. The CL value may account for a delay time between when a memory receives a READ command and when the output buffer 195 provides read data responsive to the READ command to an output bus (e.g., via a DQ pad after the output buffer 195). The CL value may be represented as a number of clock cycles. One clock cycle can be represented by T.
However, there are side effects that increase jitter of the SCLKD signal from the command replica 121, and increased active standby current (e.g., IDD3N). In turn, the jitter in the SCLKD signal increases jitter of the DLL clock signal DllClk, which causes the decrease of the margin of RMT. Thus, higher speed of memory access enabled by adding the command replica 121 may cause a decrease in the margin of RMT, accompanied with higher power consumption.